july 2012 ? 2006 fairchild semiconductor corporation www.fairchildsemi.com nc7wv07 ? rev. 1.0.2 nc7wv07 ? tinylogic ? ulp-a dual buffer (open-drain output) nc7wv07 tinylogic ? ulp-a bual buffer (open-drain output) features ? 0.9v to 3.6v v cc supply operation ? 3.6v over-voltage tolerant i/os at v cc from 0.9v to 3.6v ? extremely high speed t pd - 1.0ns: typical for 2.7v to 3.6v v cc - 1.2ns: typical for 2.3v to 2.7v v cc - 2.0ns: typical for 1.65v to 1.95v v cc - 3.2ns: typical for 1.4v to 1.6v v cc - 6.0ns: typical for 1.1v to 1.3v v cc - 13.0ns: typical for 0.9v v cc ? power-off high-impedance inputs and outputs ? high static drive (i oh /i ol ) - ? 24ma at 3.00v v cc - ?? 18ma at 2.30v v cc - ?? 6ma at 1.65v v cc - ? 4ma at 1.4v v cc - ? 2ma at 1.1v v cc - ? 0.1ma at 0.9v v cc ? uses proprietary quiet series? noise/emi reduction circuitry ? ultra-small micropak? packages ? ultra-low dynamic power description the nc7wv07 is a dual buffer with open drain output from fairchild's ultra low power-a series of tinylogic? ulp-a is ideal for applications that require extreme high speed, high drive and low power. this product is designed for a wide low voltage operating range (0.9v to 3.6v v cc ) and applications that require more drive and speed than the tinylogic ulp series, but still offer best in class low power operation. the nc7wv07 is uniquely designed for optimized power and speed, and is fabricat ed with an advanced cmos technology to achieve high-speed operation while maintaining low cmos power dissipation. ordering information part number top mark package packing method nc7wv07p6x v07 6-lead sc70, eiaj sc-88a, 1.25mm wide 3000 units on tape & reel nc7wv07l6x bc 6-lead micropak?, 1.00mm wide 5000 units on tape & reel tinylogic? ? is a registered trademark of fair child semiconductor corporation. micropak? ? and quiet series? ? are trademarks of fairchild semiconductor corporation.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com nc7wv07 ? rev. 1.0.2 2 nc7wv07 ? tinylogic ? ulp-a dual buffer (open-drain output) battery life 700 600 500 400 300 200 100 0 0.9 1.2 ulp-a (sv) ulp (sp) uhs (sz) 1.5 1.8 2.5 3.3 5.0 battery life (days) v cc supply voltage figure 1. battery life vs. v cc supply voltage notes: 1. tinylogic ? ulp and ulp-a with up to 50% less power consum ption can extend battery life significantly. battery life ?? (v battery ?i battery ?.9)/(p device )/24hrs/day where, p device ?? (i cc ? v cc ) ?? (c pd ?? c l ) ? v cc2 ? f. 2. assumes ideal 3.6v lithium ion battery with cu rrent rating of 900mah and der ated 90% and device frequency at 10mhz, with c l =15pf load. pin configurations figure 2. sc70 (top view) figure 3. micropak (top through view) pin definitions pin # sc70 pin # micropak name description 1 1 a 1 data inputs 2 2 gnd ground 3 3 a 2 data inputs 4 4 y 2 output 5 5 v cc supply voltage 6 6 y 1 output function table inputs output a y l l h *h h=high logic level l=low logic level *h=high impedance output status (open drain)
? 2006 fairchild semiconductor corporation www.fairchildsemi.com nc7wv07 ? rev. 1.0.2 3 nc7wv07 ? tinylogic ? ulp-a dual buffer (open-drain output) absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 4.6 v v in dc input voltage -0.5 4.6 v v out dc output voltage -0.5 4.6 v i ik dc input diode current v in < 0v -50 ma i ok dc output diode current v out < 0v -50 ma i ol dc output sink current +50 ma i cc or i gnd dc v cc or ground current per supply pin 50 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature, so ldering 10 seconds +260 c p d power dissipation at +85c sc70-5 150 mw micropak-6 130 micropak2-6 120 esd human body model, jedec:jesd22-a114 4000 v charge device model, jedec:jesd22-c101 2000 recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage 0.9 3.6 v v in input voltage 0 3.6 v v out output voltage 0 3.6 v i ol output current in i ol v cc =3.0v to 3.6v +24.0 ma v cc =2.3v to 3.6v +18.0 v cc =1.65v to 1.95v +6.0 v cc =1.4v to 1.6v +4.0 v cc =1.1v to 1.3v +2.0 v cc =0.9v +0.1 t a operating temperature, free air -40 +85 c ? t/ ? v minimum input edge rate v in =0.8v to 2.0, v cc =3.0v 10 ns/v ? ja thermal resistance sc70-5 425 c/w micropak-6 500 note: 3. unused inputs must be held high or low. they may not float.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com nc7wv07 ? rev. 1.0.2 4 nc7wv07 ? tinylogic ? ulp-a dual buffer (open-drain output) dc electrical characteristics symbol parameter v cc conditions t a =25c t a =-40 to 85c units min. max. min. max. v ih high level input voltage 0.90 .65 x v cc .65 x v cc v 1.10 ?? v cc ?? 1.30 .65 x v cc .65 x v cc 1.40 ?? v cc ?? 1.60 .65 x v cc .65 x v cc 1.65 ?? v cc ?? 1.95 .65 x v cc .65 x v cc 2.30 ?? v cc ?? 2.70 1.6 1.6 2.70 ?? v cc ?? 3.60 2.0 2.0 v il low level input voltage 0.90 .35 x v cc .35 x v cc v 1.10 ?? v cc ?? 1.30 .35 x v cc .35 x v cc 1.40 ?? v cc ?? 1.60 .35 x v cc .35 x v cc 1.65 ?? v cc ?? 1.95 .35 x v cc .35 x v cc 2.30 ?? v cc ?? 2.70 0.7 0.7 2.70 ?? v cc ?? 3.60 0.8 0.8 v ol low level output voltage 0.90 i ol =100a 0.1 0.1 v 1.10 ?? v cc ?? 1.30 0.1 0.1 1.40 ?? v cc ?? 1.60 0.2 0.2 1.65 ?? v cc ?? 1.95 0.2 0.2 2.30 ?? v cc ?? 2.70 0.2 0.2 2.70 ?? v cc ?? 3.60 0.2 0.2 1.10 ? v cc ? 1.30 i ol =2ma 0.25 x v cc 0.25 x v cc 1.40 ? v cc ? 1.60 i ol =4ma 0.25 x v cc 0.25 x v cc 1.65 ? v cc ? 1.95 i ol =6ma 0.3 0.3 2.30 ? v cc ? 2.70 i ol =12ma 0.4 0.4 2.70 ? v cc ? 3.60 0.4 0.4 2.30 ? v cc ? 2.70 i ol =18ma 0.6 0.6 2.70 ? v cc ? 3.60 0.4 0.4 2.70 ? v cc ? 3.60 i ol =24ma 0.55 0.55 i in input leakage current 0.90 to 3.60 0 ? v in ? 3.60 0.1 0.5 a i off power off leakage current 0 0 ? (v in, v o ) ? 3.60 0.5 0.5 a i cc quiescent supply current 0.90 to 3.60 v in =v cc , or gnd 0.9 0.9 a v cc ? v in ? 3.6v 0.9
? 2006 fairchild semiconductor corporation www.fairchildsemi.com nc7wv07 ? rev. 1.0.2 5 nc7wv07 ? tinylogic ? ulp-a dual buffer (open-drain output) ac electrical characteristics symbol parameter v cc conditions t a =25c t a =-40 to 85c units figure min. typ. max. min. max. t pzl , t plz propagation delay 0.90 c l =15pf, r u =r d =1m ? 13 ns figure 4 figure 5 1.10 ? v cc ? 1.30 c l =15pf, r u =r d =2k ? 2.0 6.0 15.0 1.0 18.6 1.40 ? v cc ? 1.60 1.0 3.2 8.7 1.0 9.7 1.65 ? v cc ? 1.95 c l =30pf, r u =r d =500 ? 1.0 2.0 6.0 1.0 6.8 2.30 ? v cc ? 2.70 0.7 1.2 3.6 0.6 4.7 2.70 ? v cc ? 3.60 0.5 1.0 3.3 0.4 4.0 c in input capacitance 0 2 pf c out output capacitance 0 6.5 c pd power dissipation capacitance 0.90 to 3.60 v in =0v or v cc , f=10mhz 10 pf ac loadings and waveforms figure 4. ac test circuit test switch t pzl , t plz 6v at v cc =3.30.3v; v cc x 2 at v cc =0.9-2.7v figure 5. ac waveforms for inverting and non-inverting functions symbol v cc 3.3v 0.3v 2.5v 0.2v 1.8v 0.15v 1.5v 0.1v 1.2v 0.1v 0.9v v mi 1.5v v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v mo v ol + 0.30v v ol + 0.15v v ol + 0.15v v ol + 0.10v v ol + 0.10v v ol + 0.10v
? 2006 fairchild semiconductor corporation www.fairchildsemi.com nc7wv07 ? rev. 1.0.2 6 nc7wv07 ? tinylogic ? ulp-a dual buffer (open-drain output) physical dimensions detail a scale: 60x b 1.90 2.00 0.20 0.50 min 1.00 0.80 1.10 0.80 0.10 c 0.25 0.10 0.46 0.26 0.20 gage plane (r0.10) 30 0 seating plane c 0.10 0.00 notes: unless otherwise specified a) this package conforms to eiaj sc-88, 1996. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. d) drawing filename: mkt-maa06arev6 2.100.30 0.10 ab 0.65 1.30 (0.25) 0.30 0.15 1 1.25 0.10 3 1.30 0.40 min see detail a land pattern recommendation 6 a 4 c 0.65 l symm pin one figure 6. 6-lead, sc70, eiaj sc-88a, 1.25mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf . package designator tape section cavity number cavity status cover type status p6x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2006 fairchild semiconductor corporation www.fairchildsemi.com nc7wv07 ? rev. 1.0.2 7 nc7wv07 ? tinylogic ? ulp-a dual buffer (open-drain output) physical dimensions 2. dimensions are in millimeters 1. conforms to jedec standard m0-252 variation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 7. 6-lead, micropak?, 1.0mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2006 fairchild semiconductor corporation www.fairchildsemi.com nc7wv07 ? rev. 1.0.2 8 nc7wv07 ? tinylogic ? ulp-a dual buffer (open-drain output)
|
